1. Field of the Invention
Embodiments of the invention relate generally to phase-change random access memory (PRAM) devices and associated operating characteristics. More particularly, embodiments of the invention relate to PRAM devices employing write verify operations.
2. Description of Related Art
Phase-change memory devices store data using phase-change materials, such as chalcogenide, which are capable of stably transitioning between amorphous and crystalline phases. The amorphous and crystalline phases (or states) exhibit different resistance values, which are used to distinguish different logic states of memory cells in the memory devices. In particular, the amorphous phase exhibits a relatively high resistance, and the crystalline phase exhibits a relatively low resistance.
At least one type of phase-change memory device—phase-change random access memory (PRAM)—uses the amorphous state to represent a logical ‘1’ and the crystalline state to represent a logical ‘0’. In a PRAM device, the crystalline state is referred to as a “set state”, and the amorphous state is referred to as a “reset state”. Accordingly, a memory cell in a PRAM stores a logical ‘0’ by “setting” a phase-change material in the memory cell to the crystalline state, and the memory cell stores a logical ‘1’ by “resetting” the phase-change material to the amorphous state. Various PRAM devices are disclosed, for example, in U.S. Pat. Nos. 6,487,113 and 6,480,438.
The phase-change material in a PRAM is converted to the amorphous state by heating the material to above a predetermined melting temperature and then quickly cooling the material. The phase-change material is converted to the crystalline state by heating the material at another predetermined temperature below the melting temperature but above a crystallization temperature for a set period of time. Accordingly, data is written to memory cells in a PRAM by converting the phase-change material in memory cells of the PRAM between the amorphous and crystalline states using heating and cooling as described.
The phase-change material in a PRAM typically comprises a compound including germanium (Ge), antimony (Sb), and tellurium (Te), i.e., a “GST” compound. The GST compound is well suited for a PRAM because it can quickly transition between the amorphous and crystalline states by heating and cooling. Examples of other compounds that could be used for the phase-change material include, but are not limited to, 2-element compounds such as GaSb, InSb, InSe, Sb2Te3, and GeTe, 3-element compounds such as GeSbTe, GaSeTe, InSbTe, SnSb2Te4, and InSbGe, or 4-element compounds such as AgInSbTe, (GeSn)SbTe, GeSb(SeTe), and Te81Ge15Sb2S2.
The memory cells in a PRAM are commonly referred to as “phase-change memory cells”, or PRAM cells. A phase-change memory cell typically comprises a top electrode, a chalcogenide layer, a bottom electrode contact, a bottom electrode, and an access transistor. In the phase-change memory cell, the chalcogenide layer is typically the phase-change material. Accordingly, a read operation is performed on the phase-change memory cell by measuring the resistance of the chalcogenide layer, and a write operation is performed on the phase-change memory cell by heating and cooling the chalcogenide layer as described above.
In order to enhance the reliability of write operations performed in PRAM devices, a write verify operation (also called a verify read operation) is often performed before or after a write operation to detect whether selected PRAM cells are in desired states. In the write verify operation, data stored in the selected PRAM cells is read out from the selected PRAM cells as verification data. The verification data is then compared with data to be written in the selected PRAM cells (also referred to as write data).
Differences between the verification data and the write data are then used to detect PRAM cells that have not been successfully written (also referred to as “failed cells” or “failed PRAM cells”). The failed cells are then re-written using corresponding bits among the write data, while selected PRAM cells that have been successfully written-to may not be re-written with corresponding bits among the write data.
The re-writing (as well as initial writing) is generally accomplished using a plurality of write loops each preceded by a write verify operation. Typically, a write loop will only be performed if the preceding write verify operation indicates that at least one selected PRAM cell has not been successfully written with the corresponding write data.